Development and characterization of low cost ultrathin 3D interconnect

Abstract

With the economic criteria and efficiency concern increasing, abundant through-hole vertical interconnections are playing the more and more important role in this area. The properties and characterization of through-hole vertical interconnects are the key issue results in the RC delay during the reliability tests for 3D high-density module packaging. ERSO recently works mainly focuses on the investigation of the quality of low cost interconnect fabrication technology to meet the reliability requirement for 3D chip stacking interconnects. In this paper, we elucidate the interconnect technology for a stacked system in package (SiP) test vehicle. Compared to the vertical interconnects developed recently, we provide an extremely low cost solution for both of silicon hole drilling process and electrical isolation within the hole. A PCB compatible electroplating technology was followed to fill the hole and shows void-free and low resistance result during this work. The chip thickness used here can be 150/spl mu/m and down to 20 /spl mu/m and still provide outstanding interconnect reliability during bending and thermal cycling test. We confirmed that the low cost 3D interconnects are potentially candidate for 3D chip stacking packaging.