Three-dimensional Integration

Three-Dimensional Integration is a semiconductor packaging framework that enables the vertical stacking of multiple device layers or chips with through-silicon vias and interlayer interconnects, thereby achieving higher functionality density and improved electrical performance compared to planar integration.

2.1K

Publications

91.4K

Citations

7.6K

Authors

933

Institutions

Publications per year

2017–2026

408

Authors

7.6K

  1. EB
    Eric Beyne

    IMEC, Belgium

    79 publications · 3.3K citations

    33

    h-index

  2. JH
    John H. Lau

    Industrial Technology Research Institute, Taiwan

    54 publications · 3.1K citations

    28

    h-index

  3. SK
    Sung Kyu Lim

    Georgia Institute of Technology, United States

    49 publications · 2.1K citations

    27

    h-index

  4. KC
    Kuan‐Neng Chen

    National Yang Ming Chiao Tung University, Taiwan

    44 publications · 2.7K citations

    26

    h-index

  5. MK
    Mitsumasa Koyanagi

    Tohoku University, Japan

    53 publications · 2.6K citations

    25

    h-index

1–5 of 7.6K

Venues

  1. 27

    h-index

  2. Microelectronic Engineering

    48 publications · 1.9K citations

    25

    h-index

  3. IEEE Transactions on Electron Devices

    46 publications · 2.1K citations

    25

    h-index

  4. IEEE Electron Device Letters

    34 publications · 1.2K citations

    19

    h-index

  5. Applied Physics Letters

    20 publications · 1.1K citations

    18

    h-index

1–5