Very-large-scale Integration Layout
Very-Large-Scale Integration Layout is the physical design representation of a VLSI circuit that specifies the geometric placement and interconnection of devices and interconnects on a semiconductor substrate subject to electrical, performance, area, power, and manufacturability constraints.
6.8K
Publications
278.4K
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17.4K
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1.8K
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2017–2026
688
6.8K
A Regular Layout for Parallel Adders
Brent, Kung · IEEE Transactions on Computers · 1982 · 1.1K citations
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IBM (United States)
Armonk, United States
59 h-index
1K publications
51.5K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
53 h-index
495 publications
33.6K citations
University of California, Berkeley
Berkeley, United States
52 h-index
411 publications
24.7K citations
Intel (United States)
Santa Clara, United States
47 h-index
556 publications
35K citations
Carnegie Mellon University
Pittsburgh, United States
47 h-index
343 publications
21.1K citations
University of California, Los Angeles
Los Angeles, United States
46 h-index
260 publications
15.5K citations
Georgia Institute of Technology
Atlanta, United States
45 h-index
578 publications
21K citations
Stanford University
Stanford, United States
40 h-index
230 publications
16.5K citations
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440 publications · 26.1K citations
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168 publications · 10.4K citations
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189 publications · 11.2K citations
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94 publications · 8.2K citations
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151 publications · 7.9K citations
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