Very-large-scale Integration Layout

Very-Large-Scale Integration Layout is the physical design representation of a VLSI circuit that specifies the geometric placement and interconnection of devices and interconnects on a semiconductor substrate subject to electrical, performance, area, power, and manufacturability constraints.

6.8K

Publications

278.4K

Citations

17.4K

Authors

1.8K

Institutions

Publications per year

2017–2026

688

Authors

17.4K

  1. AB
    Andrew B. Kahng

    University of California San Diego, United States

    81 publications · 4.6K citations

    35

    h-index

  2. SK
    Sung Kyu Lim

    Georgia Institute of Technology, United States

    89 publications · 3.2K citations

    35

    h-index

  3. DZ
    David Z. Pan

    The University of Texas at Austin, United States

    71 publications · 2.7K citations

    32

    h-index

  4. YC
    Yao‐Wen Chang

    National Taiwan University, Taiwan

    77 publications · 3K citations

    30

    h-index

  5. BY
    Bei Yu

    Chinese University of Hong Kong, Hong Kong SAR China

    54 publications · 1.6K citations

    28

    h-index

1–5 of 17.4K

Venues

  1. 80

    h-index

  2. IEEE Journal of Solid-State Circuits

    168 publications · 10.4K citations

    57

    h-index

  3. IEEE Transactions on Electron Devices

    189 publications · 11.2K citations

    53

    h-index

  4. IEEE Transactions on Computers

    94 publications · 8.2K citations

    44

    h-index

  5. 41

    h-index

1–5