Clock Tree Synthesis

Clock Tree Synthesis is a physical design methodology in Very-Large-Scale Integration that constructs a hierarchical clock distribution network to minimize skew, latency, and jitter by strategically inserting buffers and inverters while balancing routing resources and timing constraints across the chip.

143

Publications

4.3K

Citations

343

Authors

100

Institutions

Publications per year

2017–2026

Parents

Application-specific Integrated CircuitsClock Distribution NetworksClock ManagementPhysical DesignVery-large-scale Integration Layout

Publications

143

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Kimiyoshi Usami, M. Igarashi, F. Minami et al. · IEEE Journal of Solid-State Circuits · 1998 · 276 citations

Engineering, Computer Engineering, Electrical Engineering +17

Zero-skew clock routing trees with minimum wirelength

Kenneth D. Boese, Andrew B. Kahng · 2003 · 222 citations

Engineering, Computer Engineering, Electrical Engineering +17

Toward an Open-Source Digital Flow

Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça et al. · 2019 · 165 citations · Full text

Engineering, Computer Engineering, Computer Science +17

Clock-tree power optimization based on RTL clock-gating

Monica Donno, Alessandro Ivaldi, Luca Benini et al. · 2003 · 105 citations

Engineering, Computer Engineering, Computer Science +17

Low-power clock distribution using multiple voltages and reduced swings

Jatuchai Pangjun, Sachin S. Sapatnekar · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2002 · 102 citations

Engineering, Computer Engineering, Electrical Engineering +17

1–5 of 143

Authors

343

SK
Sung Kyu Lim
Georgia Institute of Technology, United States
9 publications · 345 citations
10
h-index
AB
Andrew B. Kahng
University of California San Diego, United States
7 publications · 490 citations
8
h-index
TK
Taewhan Kim
Seoul National University, South Korea
7 publications · 139 citations
7
h-index
XZ
Xin Zhao
Georgia Institute of Technology, United States
7 publications · 230 citations
7
h-index
EG
Eby G. Friedman
University of Rochester, United States
5 publications · 204 citations
7
h-index

1–5 of 343

Institutions

100

1–8 of 100

Venues

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
14 publications · 320 citations
12
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
7 publications · 293 citations
7
h-index
IEEE Transactions on Applied Superconductivity
5 publications · 271 citations
5
h-index
International Conference on Computer Aided Design
Conference · 3 publications · 118 citations
3
h-index
ACM Transactions on Design Automation of Electronic Systems
TODAES · 3 publications · 64 citations
3
h-index

1–5