Chip Partitioning

Chip Partitioning is a VLSI design methodology that decomposes a large-scale integrated circuit into smaller, manageable subcircuits or modules, based on functional, physical, or routing constraints, to facilitate hierarchical design, improve optimization efficiency, and enable parallel implementation across design teams or tools.

339

Publications

16K

Citations

685

Authors

229

Institutions

Publications per year

2017–2026

Parents

Very-large-scale Integration Layout

Publications

339

New spectral methods for ratio cut partitioning and clustering

L. Hagen, Andrew B. Kahng · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1992 · 1.3K citations

Engineering, Computer Engineering, Computer Science +15

Hierarchical Partitioning

Albert Chevan, Michael R. Sutherland · The American Statistician · 1991 · 743 citations

Engineering, Computer Engineering, Electrical Engineering +17

On a Pin Versus Block Relationship For Partitions of Logic Graphs

B. S. Landman, R.L. Russo · IEEE Transactions on Computers · 1971 · 715 citations

Engineering, Computer Engineering, Computer Science +15

GORDIAN: VLSI placement by quadratic programming and slicing optimization

Jürgen M. Kleinhans, Georg Sigl, Frank Johannes et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1991 · 533 citations

Engineering, Computer Engineering, Computer Science +16

Hierarchical Partitioning

Albert Chevan, M. Sutherland · The American Statistician · 1991 · 446 citations

Engineering, Computer Engineering, Electrical Engineering +17

1–5 of 339

Authors

685

AB
Andrew B. Kahng
University of California San Diego, United States
22 publications · 2.8K citations
17
h-index
SK
Sung Kyu Lim
Georgia Institute of Technology, United States
16 publications · 801 citations
15
h-index
IL
Igor L. Markov
University of Michigan, United States
11 publications · 1.1K citations
11
h-index
CC
Chung‐Kuan Cheng
University of California San Diego, United States
8 publications · 545 citations
8
h-index
SD
Shantanu Dutt
University of Illinois Chicago, United States
8 publications · 368 citations
8
h-index

1–5 of 685

Institutions

229

1–8 of 229

Venues

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
38 publications · 3.4K citations
23
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
12 publications · 321 citations
11
h-index
IEEE Transactions on Computers
7 publications · 1.5K citations
7
h-index
European Design Automation Conference
Conference · 6 publications · 94 citations
6
h-index
Design Automation Conference
Conference · 5 publications · 171 citations
5
h-index

1–5