Chung‐Kuan Cheng - Concepedia

Author

Chung‐Kuan Cheng

University of California San Diego ORCID

Also Known As

C. K. Cheng, C.-K. CHENG, C.-K. Cheng, C.K. Cheng, C.‐K. Cheng, CHUNG-KUAN CHENG, Cheng, Chung-Kuan, Chuanliang Cheng, Chung-Kuan CHENG, Chung-Kuan Cheng

422

Publications

7.1K

Citations

H-Index

254

Concepts

All Affiliations

University of California San Diego Tsinghua University University of Hong Kong Cadence Design Systems (United States)University of California, Berkeley

About

Chung‐Kuan Cheng is an author at University of California San Diego specializing in engineering, computer engineering, and computer science.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	37	142	5.5K
2	Education	7	7	194
3	Business	3	3	76
4	Health Sciences	3	3	96
5	Language Studies	1	1	14

Chung‐Kuan Cheng

172

Publications

6.4K

Citations

H-Index

Page 1

	Year	Citations
An O-tree representation of non-slicing floorplan and its applications Pei-Ning Guo, Chung‐Kuan Cheng, Takeshi Yoshimura Geometric ModelingMathematical ProgrammingEngineeringGeometric AlgorithmNatural Sciences	1999	376
Ratio cut partitioning for hierarchical designs Y.-C. Wei, Chung‐Kuan Cheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Mathematical ProgrammingEngineeringVlsi DesignElectronic Design AutomationComputer-aided Design	1991	240
Optimal wire sizing and buffer insertion for low power and a generalized delay model John Lillis, Chung‐Kuan Cheng, Tao Lin IEEE Journal of Solid-State Circuits Buffer DelayElectrical EngineeringEngineeringVlsi DesignUltra-low Latency	1996	234
RePlAce: Advancing Solution Quality and Routability Validation in Global Placement Chung‐Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Software MaintenanceSoftware Development PracticeLarge-scale Global OptimizationEngineeringAdvanced Computing	2018	212
Module Placement Based on Resistive Network Optimization Chung‐Kuan Cheng, E.S. Kuh IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Module PlacementElectrical EngineeringPhysical Design (Electronics)EngineeringVlsi Design	1984	194
Towards efficient hierarchical designs by ratio cut partitioning Y.-C. Wei, Chung‐Kuan Cheng EngineeringComputer-aided DesignStructural OptimizationDiscrete OptimizationRatio Cut Partitioning	2003	157
An improved two-way partitioning algorithm with stable performance (VLSI) Chung‐Kuan Cheng, Y.-C. Wei IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Cluster ComputingEngineeringComputer ArchitectureComputational ComplexityHardware Systems	1991	148
ePlace Jingwei Lu, Pengwen Chen, Chin-Chih Chang, ACM Transactions on Design Automation of Electronic Systems Numerical AnalysisLarge-scale Global OptimizationComputational ScienceNumerical ComputationEngineering	2015	145
ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits Jingwei Lu, Hao Zhuang, Pengwen Chen, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Numerical AnalysisMixed-size CircuitsElectrical EngineeringPhysical Design (Electronics)Engineering	2015	120
New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing John Lillis, Chung‐Kuan Cheng, Ting-Ting Y. Lin,	1996	103

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