Electromigration-aware Layout
Electromigration-Aware Layout is a specialized integrated circuit physical design methodology that systematically incorporates current density limits and material transport effects into layout synthesis to mitigate time-dependent degradation caused by electromigration in very-large-scale integration systems.
88
Publications
2.4K
Citations
357
Authors
105
Institutions
Publications per year
2017–2026
11
88
1–5 of 88
357
11
h-index
5
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5
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105
Technische Universität Dresden
Dresden, Germany
8 h-index
11 publications
463 citations

National Yang Ming Chiao Tung University
Hsinchu, Taiwan
7 h-index
17 publications
290 citations
Robert Bosch (Germany)
Stuttgart, Germany
6 h-index
10 publications
236 citations
Instituto de Telecomunicações
Lisbon, Portugal
4 h-index
15 publications
432 citations
Instituto Superior Técnico
Lisbon, Portugal
4 h-index
15 publications
400 citations
Texas Instruments (United States)
Dallas, United States
4 h-index
11 publications
169 citations
Stanford University
Stanford, United States
3 h-index
6 publications
140 citations
IMEC
Leuven, Belgium
3 h-index
17 publications
619 citations
1–8 of 105
6 publications · 233 citations
6
h-index
4 publications · 79 citations
4
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3 publications · 36 citations
3
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JEM · 2 publications · 24 citations
2
h-index
2 publications · 66 citations
2
h-index
1–5