Electromigration-aware Layout

Electromigration-Aware Layout is a specialized integrated circuit physical design methodology that systematically incorporates current density limits and material transport effects into layout synthesis to mitigate time-dependent degradation caused by electromigration in very-large-scale integration systems.

88

Publications

2.4K

Citations

357

Authors

105

Institutions

Publications per year

2017–2026

11

Authors

357

  1. JL
    Jens Lienig

    Technische Universität Dresden, Germany

    12 publications · 447 citations

    11

    h-index

  2. NH
    Nuno Horta

    Instituto de Telecomunicações, Portugal

    5 publications · 134 citations

    5

    h-index

  3. RM
    Ricardo Martins

    Instituto de Telecomunicações, Portugal

    5 publications · 134 citations

    5

    h-index

  4. NL
    Nuno Lourenço

    Instituto de Telecomunicações, Portugal

    5 publications · 134 citations

    5

    h-index

  5. GJ
    Göran Jerke

    Robert Bosch (Germany), Germany

    4 publications · 87 citations

    4

    h-index

1–5 of 357

Venues

  1. Microelectronics Reliability

    6 publications · 233 citations

    6

    h-index

  2. Thin Solid Films

    4 publications · 79 citations

    4

    h-index

  3. IEEE Transactions on Electron Devices

    3 publications · 36 citations

    3

    h-index

  4. Journal of Electronic Materials

    JEM · 2 publications · 24 citations

    2

    h-index

  5. Solid-State Electronics

    2 publications · 66 citations

    2

    h-index

1–5