Floorplanning

Floorplanning is a key physical design phase in the hierarchical design of digital integrated circuits, specifically within very-large-scale integration layout, that determines the approximate positions of circuit components, blocks, and interconnects on a chip to optimize area, performance, and routability while adhering to design constraints.

522

Publications

22.6K

Citations

981

Authors

266

Institutions

Publications per year

2017–2026

42

Authors

981

  1. MD
    Martin D. F. Wong

    University of Illinois Urbana-Champaign, United States

    39 publications · 2.2K citations

    24

    h-index

  2. YC
    Yao‐Wen Chang

    National Taiwan University, Taiwan

    28 publications · 1.3K citations

    21

    h-index

  3. EF
    Evangeline F. Y. Young

    Chinese University of Hong Kong, Hong Kong SAR China

    22 publications · 611 citations

    18

    h-index

  4. CC
    Chris Chu

    Iowa State University, United States

    18 publications · 710 citations

    16

    h-index

  5. CC
    Chung‐Kuan Cheng

    University of California San Diego, United States

    19 publications · 1.1K citations

    15

    h-index

1–5 of 981

Venues

  1. 33

    h-index

  2. 17

    h-index

  3. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 10 publications · 292 citations

    10

    h-index

  4. International Conference on Computer Aided Design

    Conference · 9 publications · 297 citations

    9

    h-index

  5. Integration

    8 publications · 211 citations

    8

    h-index

1–5