Current Status of Research and Development for Three-Dimensional Chip Stack Technology

TLDR

The 1999 national Ultra High‑Density Electronic System Integration project is the first initiative targeting the niche area between electronic devices and systems. The paper aims to develop technologies that overcome performance limitations of electronic systems and presents the current status of the V‑STACK 3D stacking technology. The approach focuses on 3D LSI chip stacking, optoelectronics hybrid integration, and optimal circuit design, with the chip‑based stacking technology undergoing development through wafer preparation, thinning, stacking, and inspection/testing.

Abstract

The national project of “Ultra High-Density Electronic System Integration” was initiated in 1999. This is the first project to focus on a niche area between electronic devices and systems. It aims to develop technologies for overcoming the problems in terms of performance of electronic systems. Three-dimensional (3D) LSI chip stacking, optoelectronics hybrid integration, and optimum circuit design are the technology categories. For the 3D stacking technology, a chip-based stacking technology is under extensive development that includes wafer preparation for chip stacking, wafer thinning, chip stacking, and inspection and testing. In this paper, the current development status of the 3D stacking technology, called V-STACK technology, is introduced.