M. Hoshino

Current Status of Research and Development for Three-Dimensional Chip Stack Technology

Kenji Takahashi, Hiroshi Terao, Yoshihiro TOMITA et al. · Japanese Journal of Applied Physics · 2001 · 175 citations

Engineering, Electrical Engineering, Microelectronics +12

High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking

Jian‐Jun Sun, Kazuo Kondo, Takuji Okamura et al. · Journal of The Electrochemical Society · 2003 · 148 citations · Full text

Engineering, Materials Engineering, Materials Science +15

Process integration of 3D chip stack with vertical interconnection

Kenji Takahashi, Yuichi Taguchi, M. Tomisaka et al. · 2004 · 84 citations

Engineering, Electrical Engineering, Materials Engineering +17

High-performance vertical interconnection for high-density 3D chip stacking package

M. Umemoto, Kazumasa Tanida, Y. Nemoto et al. · 2004 · 74 citations

Engineering, Computer Engineering, Electrical Engineering +17

Plasma‐Enhanced Chemical Vapor Deposition of Fluorocarbon Films with High Thermal Resistance and Low Dielectric Constants

Shunsaku Takeishi, Hiroshi Kudo, R. Shinohara et al. · Journal of The Electrochemical Society · 1997 · 48 citations

Natural Sciences, Materials Engineering, Materials Science +17