Process integration of 3D chip stack with vertical interconnection

Abstract

We succeeded in developing high-speed electrodeposition and high-rate CMP processes that greatly reduced the cost of Cu through-via fabrication used for three-dimensional (3D) chip stacking. Thin-wafer-handling processes were integrated with the development of wafer bonding and debonding equipment and processes. The investigation of thermal characteristics revealed the important structural guidelines for heat dissipation. Finally, the difficult challenges of 3D chip stacking, cost issues, wafer-handling issues and thermal issues, as well as fine pitch interconnection and electrical performance evaluation, have been established. Part of the achievements were applied to practical use in a commercial application.