Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development

Abstract

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today's advanced MCMs. This technology overcomes the RC delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and 3-D stacking technology have the potential to significantly reduce the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. However, even though TSVs have great potential, there are many fabrication issues that must be considered. The rationale for systems based on TSVs, and a fabrication process development plan for the creation of these structures, was presented by S. Spiesshoefer et al. (see ECTC Proc., p.631-33, 2003). The development plan included five main areas for TSV fabrication: formation of the blind vias, deposition of the insulation and seed layers, copper plating, wafer thinning, and wafer backside processing. The project goal is to create high aspect ratio vias four to six microns in diameter on 20-micron pitch in wafers that are subsequently thinned to a thickness of 15 to 20 microns. This paper will discuss the results obtained during the TSV fabrication in detail and explain the process development decisions that were made.