2010 · 78 citations · 12 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSystem-on-chip DesignBuilt-in Self-testClock GatingClock ManagementComputer-based TestingDesign For TestabilityTiming AnalysisAt-speed TestingAutomatic Test Pattern GenerationOn-chip Test Pattern GenerationScan Chain DesignScan Chain TestingScan DesignScan SpeedSwitching Activity Analysis
This paper presents a novel method to generate test vectors that mimic functional operation from switching activity point of view. The method uses states obtained by applying a number of functional clock cycles starting from the scan-in state of a test vector to fill the unspecified scan cell values in test cubes. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.
12
A case study of ir-drop in structured at-speed testing
J. Saxena, Kenneth M. Butler, Vinay Jayaram et al. · 2004 · 403 citations
Engineering, Computer Engineering, Electrical Engineering +14
Too much delay fault coverage is a bad thing
Jeff Rearick · 2002 · 264 citations
Engineering, Computer Engineering, Electrical Engineering +17
Impact of multiple-detect test patterns on product quality
Brady Benware, Chris Schuermyer, N. Tamarapalli et al. · 2004 · 159 citations
Management, Manufacturing Engineering, Quality Assurance +13