Design For Testability
Design for Testability is a design methodology in integrated circuit development that belongs to the class of design optimization techniques and is distinguished by its focus on embedding structural features to facilitate efficient fault detection and diagnosis during manufacturing testing.
11K
Publications
433.2K
Citations
17.3K
Authors
2.5K
Institutions
Publications per year
2017–2026
870
11K
Combinational profiles of sequential benchmark circuits
F. Brglez, D. Bryan, Krzysztof Koźmiński · 2003 · 2.1K citations
Akers · IEEE Transactions on Computers · 1978 · 1.8K citations
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University of California, Santa Barbara, United States
138 publications · 6.1K citations
43
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1–5 of 17.3K
2.5K
Intel (United States)
Santa Clara, United States
61 h-index
683 publications
34.5K citations
IBM (United States)
Armonk, United States
61 h-index
658 publications
36.7K citations
University of Illinois Urbana-Champaign
Urbana, United States
57 h-index
388 publications
20.7K citations
University of Iowa
Iowa City, United States
55 h-index
480 publications
21.8K citations
Stanford University
Stanford, United States
54 h-index
350 publications
18.8K citations
AT&T (United States)
Bedminster, United States
53 h-index
280 publications
17.5K citations
The University of Texas at Austin
Austin, United States
53 h-index
374 publications
18.6K citations
Duke University
Durham, United States
52 h-index
419 publications
16.5K citations
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617 publications · 31.1K citations
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425 publications · 29K citations
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254 publications · 14.3K citations
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218 publications · 7.3K citations
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151 publications · 6.7K citations
44
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