Irith Pomeranz - Concepedia

Author

Irith Pomeranz

University of Iowa ORCID

Also Known As

I Pomeranz, I. POMERANZ, I. Pomeranz, I.. Pomeranz, Irith Pomeranz, Pomeranz, Irith

807

Publications

10.9K

Citations

H-Index

141

Concepts

All Affiliations

University of Iowa Purdue University West Lafayette Intel (United States)Mentor Technologies

About

Irith Pomeranz is an author at University of Iowa specializing in computer engineering, engineering, and software testing.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	48	250	9.1K
2	Education	3	3	84
3	Medicine	2	2	31
4	Business	1	1	17
5	Public Health	1	1	10

Irith Pomeranz

265

Publications

9.5K

Citations

H-Index

Page 1

	Year	Citations
Techniques for minimizing power dissipation in scan and combinational circuits during test application V. Dabholkar, S. Chakravarty, Irith Pomeranz, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Electrical EngineeringEngineeringCircuit DesignTest ApplicationPower Optimization (Eda)	1998	317
Transient-fault recovery for chip multiprocessors Mohamed Gomaa, Chad Scarbrough, T. N. Vijaykumar, Transient-fault RecoveryEngineeringComputer ArchitecturePreviously-proposed CrtFault Tolerance	2003	307
Transient-fault recovery using simultaneous multithreading T.N. Vijaykumar, Irith Pomeranz, Karl Cheng ACM SIGARCH Computer Architecture News Transient-fault RecoveryEngineeringComputer ArchitectureFault ToleranceMultithreading (Computer Architecture)	2002	261
COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS Irith Pomeranz, Lakshmi Reddy, S.M. Reddy Circuit ComplexityEngineeringVerificationFormal VerificationComputational Testing	2005	260
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Proceedings/Proceedings - International Test Conference EngineeringElectronic Design AutomationComputer ArchitectureComputer-aided DesignHardware Security	2006	236
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits Seiji Kajihara, Irith Pomeranz, K. Kinoshita, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringVerificationTest Data GenerationFormal VerificationNew Test Vector	1995	222
COMPACTEST: a method to generate compact test sets for combinational circuits Irith Pomeranz, Lakshmi Reddy, S.M. Reddy IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Circuit ComplexityEngineeringCombinational CircuitsHardware SystemsFormal Verification	1993	214
Transient-fault recovery using simultaneous multithreading T.N. Vijaykumar, Irith Pomeranz, Karl Cheng Transient-fault RecoveryEngineeringComputer ArchitectureFault ToleranceMultithreading (Computer Architecture)	2003	152
On static compaction of test sequences for synchronous sequential circuits Irith Pomeranz, S.M. Reddy EngineeringMem TestingVerificationClock SynchronizationFormal Verification	1996	119
Vector restoration based static compaction of test sequences for synchronous sequential circuits Irith Pomeranz, S.M. Reddy EngineeringMem TestingTest CoverageTest SequencesFault Analysis	2002	112

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