2005 · 261 citations · 22 references
EngineeringComputer EngineeringComputer ScienceAlgorithmsDesign AutomationTest ConstructionBuilt-in Self-testCombinational Logic DescriptionDesign For TestabilityDigital Logic DesignLogic SynthesisAutomatic Test Pattern GenerationCombinational Circuit OptimizationCombinational Logic DesignCombinational Logic SynthesisFault CoverageStuck-at Fault Testing
Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. The heuristics can be added to existing test pattern generators without compromising fault coverage. Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCAS-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposed heuristics. >
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Combinational profiles of sequential benchmark circuits
F. Brglez, D. Bryan, Krzysztof Koźmiński · 2003 · 2.1K citations