S.M. Reddy

On Delay Fault Testing in Logic Circuits

Chin Jen Lin, S.M. Reddy · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1987 · 562 citations

Engineering, Computer Engineering, Electrical Engineering +16

Techniques for minimizing power dissipation in scan and combinational circuits during test application

V. Dabholkar, S. Chakravarty, Irith Pomeranz et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1998 · 320 citations

Engineering, Computer Engineering, Computer Science +17

Easily Testable Realizations ror Logic Functions

S.M. Reddy · IEEE Transactions on Computers · 1972 · 278 citations

Engineering, Computer Engineering, Computer Science +13

COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS

Irith Pomeranz, Lakshmi Reddy, S.M. Reddy · 2005 · 261 citations

Engineering, Computer Engineering, Computer Science +14

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

Santiago Remersaro, Xijiang Lin, Zhuo Zhang et al. · Proceedings/Proceedings - International Test Conference · 2006 · 239 citations

Engineering, Computer Engineering, Electrical Engineering +17