Techniques for minimizing power dissipation in scan and combinational circuits during test application

TLDR

Power dissipation during test of scan and BIST‑tested combinational circuits is a significant issue. The study proposes heuristics to mitigate power‑dissipation problems during test. The authors show that the power‑dissipation problems are intractable, but heuristics with provable bounds can be derived for BIST‑tested combinational circuits, achieving substantial power savings in experiments.

Abstract

Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using built-in self-test (BIST). The problems are shown to be intractable. Heuristics to solve these problems are discussed. We show that heuristics with good performance bounds can be derived for combinational circuits tested using BIST. Experimental results show that considerable reduction in power dissipation can be obtained using the proposed techniques.