Built-in Self-test
Built-In Self-Test is a design-for-testability technique in System-On-Chip and VLSI design that integrates dedicated on-chip hardware to autonomously perform testing of integrated circuits, distinguishing itself by enabling in-situ fault detection without external test equipment.
5.1K
Publications
195.7K
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8.5K
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Publications per year
2017–2026
380
5.1K
Combinational profiles of sequential benchmark circuits
F. Brglez, D. Bryan, Krzysztof Koźmiński · 2003 · 2.1K citations
Fault injection techniques and tools
Mei-Chen Hsueh, Timothy Tsai, Ravishankar K. Iyer · Computer · 1997 · 869 citations · Full text
Built-in test for VLSI: Pseudorandom techniques
Integration · 1989 · 866 citations
Engineering, Computer Engineering, Electrical Engineering +12
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Intel (United States)
Santa Clara, United States
47 h-index
341 publications
14.1K citations
University of Iowa
Iowa City, United States
43 h-index
230 publications
10.7K citations
Stanford University
Stanford, United States
41 h-index
183 publications
9.9K citations
IBM (United States)
Armonk, United States
40 h-index
350 publications
16.2K citations
University of Illinois Urbana-Champaign
Urbana, United States
39 h-index
180 publications
13.1K citations
Duke University
Durham, United States
38 h-index
219 publications
7.7K citations
The University of Texas at Austin
Austin, United States
37 h-index
151 publications
7.4K citations
Philips (Netherlands)
Amsterdam, The Netherlands
36 h-index
185 publications
9.5K citations
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199 publications · 13.8K citations
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298 publications · 14.5K citations
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155 publications · 8.8K citations
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112 publications · 4.7K citations
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134 publications · 4.5K citations
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