Built-in Self-test

Built-In Self-Test is a design-for-testability technique in System-On-Chip and VLSI design that integrates dedicated on-chip hardware to autonomously perform testing of integrated circuits, distinguishing itself by enabling in-situ fault detection without external test equipment.

5.1K

Publications

195.7K

Citations

8.5K

Authors

1.4K

Institutions

Publications per year

2017–2026

380

Authors

8.5K

  1. SR
    S.M. Reddy

    University of Iowa, United States

    115 publications · 5.4K citations

    41

    h-index

  2. KC
    Krishnendu Chakrabarty

    Duke University, United States

    133 publications · 5.1K citations

    39

    h-index

  3. EJ
    Erik Jan Marinissen

    IMEC, Belgium

    56 publications · 3.6K citations

    33

    h-index

  4. YZ
    Y. Zorian

    Cirrus Logic (United States), United States

    73 publications · 4.1K citations

    33

    h-index

  5. IP
    Irith Pomeranz

    University of Iowa, United States

    93 publications · 3.9K citations

    32

    h-index

1–5 of 8.5K

Venues

  1. IEEE Transactions on Computers

    199 publications · 13.8K citations

    63

    h-index

  2. 62

    h-index

  3. IEEE Design & Test of Computers

    155 publications · 8.8K citations

    51

    h-index

  4. IEEE Transactions on Nuclear Science

    112 publications · 4.7K citations

    38

    h-index

  5. 37

    h-index

1–5