A logic design structure for LSI testability

Abstract

The ability to put hundreds of logic gates on a single chip of silicon offers great potential for reducing power, increasing speed, and reducing cost. Unfortunately, several problems must be solved in order to exploit these advantages of large-scale integration, LSI. This paper will describe a logic design method that will greatly simplify problems in testing, diagnostics, and field service for LSI. The design method is based on two concepts that are nearly independent but combine efficiently and effectively. The first is to design sequential logic structures so that correct operation is not dependent on signal rise and fall time or on circuit or wire delay. The second is to design all the internal storage elements (other than memory arrays) so that they can also be operated as shift registers to facilitate testing and diagnostics. Sequential logic, which is difficult to test, can then be transformed to combinational logic, which is less difficult. The transformation is performed during test generation. Advantages and cost impact will also be discussed qualitatively.