Logic Synthesis

Logic Synthesis is an electronic design automation process that transforms an abstract behavioral or register-transfer level specification of digital circuitry into an optimized, technology-mapped gate-level implementation that satisfies given functional and design constraints.

7.7K

Publications

345.2K

Citations

12K

Authors

2.1K

Institutions

Publications per year

2017–2026

917

Authors

12K

  1. RK
    Robert K. Brayton

    University of California, Berkeley, United States

    126 publications · 9.4K citations

    46

    h-index

  2. AS
    Alberto Sangiovanni‐Vincentelli

    University of California, Berkeley, United States

    101 publications · 9.4K citations

    44

    h-index

  3. RD
    Rolf Drechsler

    University of Bremen, Germany

    124 publications · 5.5K citations

    43

    h-index

  4. GD
    Giovanni De Micheli

    École Polytechnique Fédérale de Lausanne, Switzerland

    103 publications · 4.6K citations

    37

    h-index

  5. RW
    Robert Wille

    Johannes Kepler University of Linz, Austria

    69 publications · 3.8K citations

    35

    h-index

1–5 of 12K

Venues

  1. 89

    h-index

  2. IEEE Transactions on Computers

    321 publications · 27K citations

    64

    h-index

  3. 38

    h-index

  4. International Conference on Computer Aided Design

    Conference · 57 publications · 3.3K citations

    32

    h-index

  5. IEEE Transactions on Electronic Computers

    82 publications · 3.6K citations

    31

    h-index

1–5