Arithmetic Circuit Synthesis
Arithmetic Circuit Synthesis is a specialized method within logic synthesis that focuses on the automated construction of digital circuits designed to perform arithmetic operations by optimizing structural and functional representations according to specified performance metrics.
514
Publications
18.7K
Citations
1K
Authors
404
Institutions
Publications per year
2017–2026
66
Parents
514
1–5 of 514
1K
11
h-index
8
h-index
7
h-index
École Polytechnique Fédérale de Lausanne, Switzerland
7 publications · 213 citations
7
h-index
7
h-index
1–5 of 1K
404
École Polytechnique Fédérale de Lausanne
Lausanne, Switzerland
14 h-index
42 publications
1.3K citations

Centre National de la Recherche Scientifique
Paris, France
11 h-index
23 publications
741 citations
Nanyang Technological University
Singapore, Singapore
10 h-index
22 publications
483 citations
The University of Texas at Austin
Austin, United States
10 h-index
24 publications
991 citations
Shahid Beheshti University
Tehran, Iran
10 h-index
17 publications
495 citations
University of California, Los Angeles
Los Angeles, United States
9 h-index
15 publications
1.3K citations
IBM (United States)
Armonk, United States
8 h-index
11 publications
493 citations

École Normale Supérieure de Lyon
Lyon, France
8 h-index
17 publications
613 citations
1–8 of 404
43 publications · 2K citations
24
h-index
18 publications · 958 citations
15
h-index
11 publications · 417 citations
11
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10 publications · 210 citations
10
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9 publications · 319 citations
9
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1–5