And-inverter Graph Optimization
And-Inverter Graph Optimization is a logic synthesis technique that refines Boolean logic representations by restructuring and minimizing And-Inverter Graphs through node rewriting, resubstitution, and technology mapping to achieve area, delay, or power improvements in digital circuit design.
16
Publications
1.2K
Citations
42
Authors
17
Institutions
Publications per year
2017–2026
5
Parents
16
SAT sweeping with local observability don't-cares
Qi Zhu, Nathan Kitchen, Andreas Kuehlmann et al. · 2006 · 90 citations
1–5 of 16
42
École Polytechnique Fédérale de Lausanne, Switzerland
6 publications · 399 citations
6
h-index
5
h-index
4
h-index
École Polytechnique Fédérale de Lausanne, Switzerland
4 publications · 281 citations
4
h-index
2
h-index
1–5 of 42
17
École Polytechnique Fédérale de Lausanne
Lausanne, Switzerland
5 h-index
12 publications
928 citations
University of California, Berkeley
Berkeley, United States
4 h-index
13 publications
2.1K citations
Cadence Design Systems (United States)
San Jose, United States
2 h-index
2 publications
121 citations
University of Bremen
Bremen, Germany
2 h-index
3 publications
171 citations
University of Utah
Salt Lake City, United States
2 h-index
6 publications
314 citations

Lawrence Berkeley National Laboratory
Berkeley, United States
2 h-index
2 publications
121 citations

University of Naples Federico II
Naples, Italy
1 h-index
4 publications
92 citations
Universidade Federal do Rio Grande do Sul
Porto Alegre, Brazil
1 h-index
3 publications
42 citations
1–8 of 17
2 publications · 288 citations
2
h-index
2 publications · 116 citations
2
h-index
Repository · 1 publications · 13 citations
1
h-index
ITETBT · 1 publications · 23 citations
1
h-index
1 publications · 34 citations
1
h-index
1–5