Area Optimization
Area Optimization is a design methodology aimed at minimizing the physical footprint of digital circuits, particularly in high-level synthesis, logic synthesis, lookup table configuration, and standard cell design, by applying algorithmic and structural transformations that reduce resource utilization without compromising functional correctness or performance constraints.
572
Publications
21.1K
Citations
1.4K
Authors
411
Institutions
Publications per year
2017–2026
77
Variants
Area Minimization
572
1–5 of 572
1.4K
University of Illinois Urbana-Champaign, United States
17 publications · 575 citations
15
h-index
13
h-index
10
h-index
University of California, Berkeley, United States
9 publications · 1K citations
9
h-index
8
h-index
1–5 of 1.4K
411
University of California, Berkeley
Berkeley, United States
17 h-index
41 publications
2.9K citations
University of California, Los Angeles
Los Angeles, United States
17 h-index
50 publications
2K citations
The University of Texas at Austin
Austin, United States
14 h-index
37 publications
1.3K citations
University of California San Diego
San Diego, United States
13 h-index
28 publications
1.1K citations
University of Illinois Urbana-Champaign
Urbana, United States
13 h-index
33 publications
771 citations
University of Southern California
Los Angeles, United States
12 h-index
29 publications
875 citations
Carnegie Mellon University
Pittsburgh, United States
12 h-index
32 publications
714 citations
Iowa State University
Ames, United States
12 h-index
22 publications
534 citations
1–8 of 411
60 publications · 3.5K citations
31
h-index
Conference · 16 publications · 890 citations
14
h-index
11 publications · 673 citations
11
h-index
Conference · 8 publications · 168 citations
8
h-index
5 publications · 195 citations
5
h-index
1–5