Standard Cell Design
Standard Cell Design is a methodology in VLSI design that belongs to the class of integrated circuit layout techniques and is distinguished by the use of pre-characterized, reusable logic cells with uniform physical configurations to enable automated, high-density, and timing-predictable synthesis of digital circuits.
850
Publications
32.5K
Citations
2.4K
Authors
450
Institutions
Publications per year
2017–2026
135
850
FreePDK: An Open-Source Variation-Aware Design Kit
James E. Stine, Ivan D. Castellanos, Michael Wood et al. · 2007 · 429 citations
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2.4K
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450
University of Illinois Urbana-Champaign
Urbana, United States
20 h-index
79 publications
2.7K citations
Cadence Design Systems (United States)
San Jose, United States
18 h-index
47 publications
2.9K citations
University of California San Diego
San Diego, United States
18 h-index
62 publications
2.9K citations
IBM (United States)
Armonk, United States
18 h-index
95 publications
3.2K citations
IMEC
Leuven, Belgium
18 h-index
277 publications
13.1K citations
The University of Texas at Austin
Austin, United States
17 h-index
70 publications
2K citations

National Taiwan University
Taipei, Taiwan
15 h-index
39 publications
1.1K citations
Intel (United States)
Santa Clara, United States
15 h-index
56 publications
1.9K citations
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55 publications · 3.8K citations
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34 publications · 3K citations
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21 publications · 643 citations
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22 publications · 471 citations
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Conference · 15 publications · 290 citations
13
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