Concepedia

Cell Footprint Optimization

Cell Footprint Optimization is a design methodology in integrated circuit physical synthesis that minimizes the area occupancy of standard cells within a fixed-height row architecture while preserving electrical performance and routability constraints.

14

Publications

405

Citations

106

Authors

17

Institutions

Publications per year

2017–2026

2

Parents

Publications

14

Engineering details of a stable force-directed placer

Kristofer Vorwerk, Andrew Kennings, Anthony Vannelli · 2005 · 61 citations

, , +16

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V$_{\rm TH}$ Read-Port, and Offset Cell VDD Biasing Techniques

Meng‐Fan Chang, Ming-Pin Chen, Lai-Fu Chen et al. · IEEE Journal of Solid-State Circuits · 2013 · 57 citations

, , +16

Miniaturized Metamaterial Absorber Using Three-Dimensional Printed Stair-Like Jerusalem Cross

Daecheon Lim, Sungwook Yu, Sungjoon Lim · IEEE Access · 2018 · 49 citations · Full text

, , +15

Ultra-high density 3D SRAM cell designs for monolithic 3D integration

Chang Liu, Sung Kyu Lim · 2012 · 39 citations

, , +17

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router

Kwangsoo Han, Andrew B. Kahng, Hyein Lee · 2015 · 31 citations

, , +16

1–5 of 14

Authors

106

  1. SK
    Sung Kyu Lim

    Georgia Institute of Technology, United States

    3 publications · 86 citations

    3

    h-index

  2. SB
    Stéphane Badel

    École Polytechnique Fédérale de Lausanne, Switzerland

    2 publications · 29 citations

    2

    h-index

  3. PV
    Paolo Vietti

    École Polytechnique Fédérale de Lausanne, Switzerland

    2 publications · 29 citations

    2

    h-index

  4. FK
    Frank K. Gürkaynak

    ETH Zurich, Switzerland

    2 publications · 29 citations

    2

    h-index

  5. AP
    Anna Peña Martinez

    École Polytechnique Fédérale de Lausanne, Switzerland

    2 publications · 29 citations

    2

    h-index

1–5 of 106

Institutions

17

  1. Georgia Institute of Technology

    Atlanta, United States

    3 h-index

    9 publications

    232 citations

  2. École Polytechnique Fédérale de Lausanne

    Lausanne, Switzerland

    1 h-index

    7 publications

    126 citations

  3. University of California San Diego

    San Diego, United States

    1 h-index

    3 publications

    93 citations

  4. Fukuoka Institute of Technology

    Fukuoka, Japan

    1 h-index

    1 publications

    57 citations

  5. IMEC

    Leuven, Belgium

    1 h-index

    17 publications

    221 citations

  6. Industrial Technology Research Institute

    Hsinchu, Taiwan

    1 h-index

    4 publications

    228 citations

  7. Intel (United States)

    Santa Clara, United States

    1 h-index

    8 publications

    160 citations

  8. National Tsing Hua University

    Hsinchu, Taiwan

    1 h-index

    6 publications

    342 citations

1–8 of 17

Venues

  1. IEEE Transactions on Electron Devices

    2 publications · 49 citations

    2

    h-index

  2. Electromagnetic waves

    PIER · 1 publications · 26 citations

    1

    h-index

  3. IEEE Journal of Solid-State Circuits

    1 publications · 57 citations

    1

    h-index

  4. IEEE Access

    1 publications · 49 citations

    1

    h-index

  5. 2008 Design, Automation and Test in Europe

    Conference · 1 publications · 11 citations

    1

    h-index

1–5