Clock Buffer Design

Clock Buffer Design is a methodological framework within standard cell design that specifically addresses the optimization of clock signal distribution by minimizing skew, delay, and power consumption through the strategic placement and sizing of buffer cells in the clock tree network.

104

Publications

3.1K

Citations

354

Authors

Institutions

Publications per year

2017–2026

Parents

Standard Cell Design

Publications

104

A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation

Mozhgan Mansuri, Chih-Kong Ken Yang · IEEE Journal of Solid-State Circuits · 2003 · 108 citations

Engineering, Electrical Engineering, Low-power Design +16

Clock-deskew buffer using a SAR-controlled delay-locked loop

Guang-Kaai Dehng, June-Ming Hsu, Ching‐Yuan Yang et al. · IEEE Journal of Solid-State Circuits · 2000 · 96 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

T. Saeki, Y. Nakaoka, Masafumi Fujita et al. · IEEE Journal of Solid-State Circuits · 1996 · 87 citations

Engineering, Computer Engineering, Electrical Engineering +14

Statistical timing analysis driven post-silicon-tunable clock-tree synthesis

Jeng-Liang Tsai, Lizheng Zhang, Charlie Chung‐Ping Chen · International Conference on Computer Aided Design · 2005 · 82 citations

Engineering, Computer Engineering, Computer Science +16

Pulsewidth control loop in high-speed CMOS clock buffers

Fenghao Mu, C. Svensson · IEEE Journal of Solid-State Circuits · 2000 · 73 citations

Engineering, Computer Engineering, Electrical Engineering +15

1–5 of 104

Authors

354

TM
T. Matano
NEC (Japan), Japan
4 publications · 178 citations
4
h-index
XZ
Xin Zhao
Georgia Institute of Technology, United States
4 publications · 102 citations
4
h-index
SK
Sung Kyu Lim
Georgia Institute of Technology, United States
4 publications · 102 citations
4
h-index
KD
K. Duraisami
Politecnico di Torino, Italy
3 publications · 103 citations
3
h-index
KK
K. Koyama
NEC (Japan), Japan
3 publications · 166 citations
3
h-index

1–5 of 354

Institutions

1–8 of 89

Venues

IEEE Journal of Solid-State Circuits
18 publications · 839 citations
17
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
5 publications · 148 citations
5
h-index
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3 publications · 115 citations
3
h-index
IEEE Transactions on Applied Superconductivity
2 publications · 31 citations
2
h-index
International Conference on Computer Aided Design
Conference · 2 publications · 116 citations
2
h-index

1–5