T. Matano

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

T. Saeki, Y. Nakaoka, Masafumi Fujita et al. · IEEE Journal of Solid-State Circuits · 1996 · 87 citations

Engineering, Computer Engineering, Electrical Engineering +14

A 1-gb/s/pin 512-mb ddrii sdram using a digital dll and a slew-rate-controlled output buffer

T. Matano, Y. Takai, T. Takahashi et al. · IEEE Journal of Solid-State Circuits · 2003 · 65 citations

Engineering, Computer Engineering, Electrical Engineering +14

A 30-ns 256-Mb DRAM with a multidivided array structure

Tadahiko Sugibayashi, T. Takeshima, I. Naritake et al. · IEEE Journal of Solid-State Circuits · 1993 · 39 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 4-level storage 4 Gb DRAM

T. Murotani, I. Naritake, T. Matano et al. · 2002 · 25 citations

Engineering, Computer Engineering, Electrical Engineering +15

A 30 ns 256 Mb DRAM with multi-divided array structure

Tadahiko Sugibayashi, T. Takeshima, I. Naritake et al. · 1993 · 18 citations

Engineering, Computer Engineering, Electrical Engineering +17