T. Saeki

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

T. Saeki, Y. Nakaoka, Masafumi Fujita et al. · IEEE Journal of Solid-State Circuits · 1996 · 87 citations

System On Chip, 256-Mb Sdram, Vlsi Design +15

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A. Tanabe, T. Takeshima, Hiroki Koike et al. · IEEE Journal of Solid-State Circuits · 1992 · 79 citations

Engineering, Emerging Memory Technology, Mem Testing +16

Resonance stub effect in a transition from a through via hole to a stripline in multilayer PCBs

Taras Kushta, Kôichi Narita, Tomoya Kaneko et al. · IEEE Microwave and Wireless Components Letters · 2003 · 65 citations

Electrical Engineering, Multilayer Pcbs, Engineering +12

A 30-ns 256-Mb DRAM with a multidivided array structure

Tadahiko Sugibayashi, T. Takeshima, I. Naritake et al. · IEEE Journal of Solid-State Circuits · 1993 · 39 citations

Engineering, Vlsi Design, Emerging Memory Technology +17

A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand"

T. Saeki, M. Mitsuishi, H. Iwaki et al. · IEEE Journal of Solid-State Circuits · 2000 · 29 citations

1.3-Cycle Lock-in Time, Engineering, Vlsi Design +15