0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation

A. Tanabe, M. Umetani, I. Fujiwara, +6

IEEE Journal of Solid-State Circuits

Low-power ElectronicsPhotonicsElectrical EngineeringDemux IcsEngineering +11

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A. Tanabe, T. Takeshima, Hiroki Koike, +16

IEEE Journal of Solid-State Circuits

EngineeringEmerging Memory TechnologyMem TestingComputer ArchitectureOpen Bit-line Readout +14

A Novel Variable Inductor Using a Bridge Circuit and Its Application to a 5–20 GHz Tunable LC-VCO

A. Tanabe, K. Hijioka, Hirokazu Nagase, +1

IEEE Journal of Solid-State Circuits

Electrical EngineeringEngineeringRadio FrequencyVariable InductanceHigh-frequency Device +6

Low-power embedded ReRAM technology for IoT applications

M. Ueki, Kazuhiro Takeuchi, Takashi Yamamoto, +15

A single-chip 2.4-Gb/s CMOS optical receiver IC with low substrate cross-talk preamplifier

A. Tanabe, M. Soda, Y. Nakahara, +3

IEEE Journal of Solid-State Circuits

Free-space Optical NetworkPhotonicsSingle-chip Receiver IcEngineering59-Db/spl Omega/ Gain +9

Low-power embedded ReRAM technology for IoT applications

M. Ueki, K. T. Akeuchi, Toru Yamamoto, +15

A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems

Y. Amamiya, Shunichi Kaeriyama, Hidemi Noguchi, +16

Low JitterVlsi DesignEngineeringComputer ArchitectureOptical Wireless Communication +15

A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems

Shunichi Kaeriyama, Yasushi Amamiya, Hidemi Noguchi, +16

IEEE Journal of Solid-State Circuits

EngineeringVlsi DesignOscillatorsComputer ArchitectureTransmitter Chip +18

A gate-side air-gap structure (GAS) to reduce the parasitic capacitance in MOSFETs

M. Togo, A. Tanabe, Akira Furukawa, +2

Device ModelingLow-power ElectronicsElectrical EngineeringEngineeringVlsi Design +11

A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC

A. Tanabe, Y. Nakahara, Akira Furukawa, +1

IEEE Journal of Solid-State Circuits

Hardware SecuritySystem On ChipEngineeringVlsi DesignVlsi Architecture +10