A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

Abstract

A 64-Mb dynamic random access memory (DRAM) with a 30-ns access time and 19.48-mm*9.55-mm die size has been developed. For reducing inter-bit-line coupling noise, the DRAM features a latched-sense, shared-sense circuit with open bit-line readout and folded bit-line rewrite operations. To reduce test costs and increase chip reliability, it has been equipped with built-in self-test and self-repair (BIST and BISR) circuits that use spare SRAM cells.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>