Y. Nakahara

A single-chip 2.4-Gb/s CMOS optical receiver IC with low substrate cross-talk preamplifier

A. Tanabe, M. Soda, Y. Nakahara et al. · IEEE Journal of Solid-State Circuits · 1998 · 51 citations

Free-space Optical Network, Photonics, Single-chip Receiver Ic +11

Power-aware 65 nm node CMOS technology using variable V/sub DD/ and back-bias control with reliability consideration for back-bias mode

M. Togo, T. Fukai, Y. Nakahara et al. · 2004 · 25 citations

Low-power Electronics, Electrical Engineering, Engineering +12

A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC

A. Tanabe, Y. Nakahara, Akira Furukawa et al. · IEEE Journal of Solid-State Circuits · 2003 · 18 citations

Hardware Security, System On Chip, Engineering +12

A 65 nm-node CMOS technology with highly reliable triple gate oxide suitable for power-considered system-on-a-chip

T. Fukai, Y. Nakahara, Masayuki Terai et al. · 2004 · 15 citations

Low-power Electronics, Electrical Engineering, Engineering +13

CMOS device optimization for system-on-a-chip applications

Kazuo Imai, Koji Yamaguchi, Tomoaki Kudo et al. · 2002 · 15 citations

Hardware Security, System On Chip, Low-power Electronics +13