IEEE Journal of Solid-State Circuits · 2003 · 18 citations · 12 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsCmos Circuit DesignCombinational Logic DescriptionDigital Integrated CircuitsDynamic Power ReductionLow-power Digital Circuit DesignMixed-signal IntegrationCmos Logic CircuitsCmos Logic DesignDemultiplexersHigh-speed Cmos DesignHigh-speed Logic DesignLow-power Logic DesignPower ConsumptionRedundant Logic Design
A redundant multivalued logic is proposed for high-speed communication ICs. In this logic, serial binary data are received and converted into parallel redundant multivalued data. Then they are restored into parallel binary data. Because of the multivalued data conversion, this logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was fabricated using a 0.18-μm CMOS process. The IC achieved an operating speed of 10 Gb/s with a supply voltage of only 1.3 V and with power consumption of 38 mW. This logic may achieve CMOS communication ICs with an operating speed several times greater than 10 Gb/s.
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A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver
R. Farjad-Rad, Chih-Kong Ken Yang, Mark Horowitz et al. · 2003 · 49 citations