CMOS device optimization for system-on-a-chip applications

Abstract

This paper describes a 0.13-/spl mu/m-generation CMOS technology optimized for system-on-a-chip (SoC) applications. The wide-range of performances obtained using a triple gate oxide and multiple threshold voltage control allows the SoC to operate at high speed with low standby power. Core CMOS transistors, which have a 1.9 nm gate oxide and a 95-nm physical gate length, show an excellent drive current of 740/335 /spl mu/A//spl mu/m at 1.2 V. Low power CMOS transistors have a standby current of only 2-0.2 pA//spl mu/m with a 2.6-nm gate oxide and a 120-nm gate length. This technology has also been used to make a 1.4-/spl mu/m/sup 2/ loadless 4T SRAM cell as well as a 2.5-/spl mu/m/sup 2/ 6T cell. The wiring RC delay has been reduced by integrating Cu interconnects with a low-k "ladder-oxide" layer.