A 30-ns 256-Mb DRAM with a multidivided array structure

Abstract

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25- mu m CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 mu m/sup 2/. Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>