IEEE Journal of Solid-State Circuits · 1996 · 87 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignClock ManagementCmos Circuit DesignEmbedded Memory BlocksIntegrated Circuit DesignMemory Subsystem DesignTiming AnalysisArray DesignClock Buffer DesignFirst-in First-out BuffersHigh-speed Cmos DesignYield Enhancement
A 256-Mb SDRAM (245.7 mm/sup 2/) has been developed using (1) a high cell occupation ratio (60.2%) array design for chip size reduction and a high yield, (2) a prefetched pipeline scheme (PPS) using a first-in first-out (FIFO) buffer with parallel serial converter for 250-MHz clock frequency operation, and (3) a synchronous mirror delay (SMD) circuit for 2.5-ns clock access and low standby current.
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A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM
T.H. Lee, Kevin Donnelly, J. Ho et al. · IEEE Journal of Solid-State Circuits · 1994 · 178 citations
Engineering, Computer Engineering, Electrical Engineering +17
A PLL clock generator with 5 to 110 MHz lock range for microprocessors
I.A. Young, J.K. Greason, J.E. Smith et al. · 2003 · 54 citations
Engineering, Computer Engineering, Electrical Engineering +12
A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay
T. Saeki, Y. Nakaoka, M. Fujita et al. · 2002 · 35 citations
Engineering, Computer Engineering, Electrical Engineering +12