K. Miyano

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

T. Saeki, Y. Nakaoka, Masafumi Fujita et al. · IEEE Journal of Solid-State Circuits · 1996 · 87 citations

Engineering, Computer Engineering, Electrical Engineering +14

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

K. Okano, T. Izumida, H. Kawasaki et al. · 2006 · 76 citations

Engineering, Electrical Engineering, Microfabrication +16

High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique

A. Oishi, Osamu Fujii, T. Yokoyama et al. · 2005 · 42 citations

Engineering, Electrical Engineering, Circuit Theory +16

A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

Nobuaki Yasutake, K. Ohuchi, M. Fujiwara et al. · 2004 · 36 citations

Engineering, Electrical Engineering, Low-power Design +16

Impact of BOX Scaling on 30 nm Gate Length FD SOI MOSFETs

M. Fujiwara, T. Morooka, Nobuaki Yasutake et al. · 2006 · 36 citations

Engineering, Computer Engineering, Electrical Engineering +16