T. Izumida

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

K. Okano, T. Izumida, H. Kawasaki et al. · 2006 · 76 citations

Electrical Engineering, Bulk Silicon Substrate, Engineering +9

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

A. Kaneko, A. Yagishita, K. Yahashi et al. · 2006 · 53 citations

Low-power Electronics, Propagation Delay Time, Electrical Engineering +10

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

Hikaru Kawasaki, K. Okano, A. Kaneko et al. · 2006 · 44 citations

Electrical Engineering, Engineering, Vlsi Design +12

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

A. Kaneko, A. Yagishita, K. Yahashi et al. · 2006 · 44 citations

Electrical Engineering, Engineering, Sidewall Transfer Process +8

Direct evaluation of DC characteristic variability in FinFET SRAM Cell for 32 nm node and beyond

S. Inaba, Hirohisa Kawasaki, Kimitoshi Okano et al. · 2007 · 16 citations

Device Modeling, Electrical Engineering, Finfet Sram +15