K. Yahashi

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

Hidetake Tanaka, M. Kido, K. Yahashi et al. · 2007 · 576 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +15

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

K. Okano, T. Izumida, H. Kawasaki et al. · 2006 · 76 citations

Electrical Engineering, Bulk Silicon Substrate, Engineering +9

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

A. Kaneko, A. Yagishita, K. Yahashi et al. · 2006 · 53 citations

Low-power Electronics, Propagation Delay Time, Electrical Engineering +10

Hydride vapor-phase epitaxy growth of high-quality GaN bulk single crystal by epitaxial lateral overgrowth

Takumi Shibata, Hiroki Sone, K. Yahashi et al. · Journal of Crystal Growth · 1998 · 45 citations

Materials Science, Epitaxial Growth, Engineering +5

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

A. Kaneko, A. Yagishita, K. Yahashi et al. · 2006 · 44 citations

Electrical Engineering, Engineering, Sidewall Transfer Process +8