2007 · 585 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringElectronic MaterialsMicroelectronicsSemiconductor DevicesDevice ScalingIntegrated Circuit DesignMemory DevicesMemory HierarchyMemory Subsystem DesignElectrode FabricationFabricationFlash MemoryFlash Memory DevicesMemory Array ArchitectureMemory Cell DesignMemory Circuit DesignNon-volatile Memory Design
We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.