Nobuaki Yasutake

A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

Nobuaki Yasutake, K. Ohuchi, M. Fujiwara et al. · 2004 · 36 citations

Engineering, Electrical Engineering, Low-power Design +16

Impact of BOX Scaling on 30 nm Gate Length FD SOI MOSFETs

M. Fujiwara, T. Morooka, Nobuaki Yasutake et al. · 2006 · 36 citations

Engineering, Computer Engineering, Electrical Engineering +16

14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide

A. Hokazono, K. Ohuchi, M. Takayanagi et al. · 2003 · 33 citations

Engineering, Electrical Engineering, Low-power Design +9

Understanding of strain effects on high-field carrier velocity in (100) and (110) CMOSFETs under quasi-ballistic transport

Masumi Saitoh, Nobuaki Yasutake, Yukio Nakabayashi et al. · 2009 · 19 citations

Engineering, Electrical Engineering, Materials Science +16

In situ Doped Embedded-SiGe Source/Drain Technique for 32 nm Node p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor

H. Okamoto, A. Hokazono, K. Adachi et al. · Japanese Journal of Applied Physics · 2008 · 16 citations

Engineering, Electrical Engineering, Materials Science +12