K. Adachi

High-resolution characterization of ultrashallow junctions by measuring in vacuum with scanning spreading resistance microscopy

L. Zhang, K. Ohuchi, K. Adachi et al. · Applied Physics Letters · 2007 · 77 citations

Engineering, Microscopy, Vacuum Device +20

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

S. Inaba, K. Okano, Shôichi Matsuda et al. · IEEE Transactions on Electron Devices · 2002 · 75 citations

Low-power Electronics, Nitrogen Concentration, Electrical Engineering +12

1-nm Spatial Resolution in Carrier Profiling of Ultrashallow Junctions by Scanning Spreading Resistance Microscopy

Li Zhang, Hiroyoshi Tanimoto, K. Adachi et al. · IEEE Electron Device Letters · 2008 · 42 citations

Nanoscale Science, Electrical Engineering, Engineering +15

A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

Nobuaki Yasutake, K. Ohuchi, M. Fujiwara et al. · 2004 · 36 citations

Low-power Electronics, Electrical Engineering, Engineering +13

14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide

A. Hokazono, K. Ohuchi, M. Takayanagi et al. · 2003 · 33 citations

Low-power Electronics, Electrical Engineering, Engineering +10