A. Oishi

High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique

A. Oishi, Osamu Fujii, T. Yokoyama et al. · 2005 · 42 citations

Engineering, Electrical Engineering, Circuit Theory +16

Mobility improvement for 45nm node by combination of optimized stress control and channel orientation design

T. Komoda, A. Oishi, T. Sanuki et al. · 2005 · 42 citations

Engineering, Electrical Engineering, Microelectronics +12

Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology

T. Sanuki, A. Oishi, Y. Morimasa et al. · 2004 · 35 citations

Engineering, Electrical Engineering, Microelectronics +16

A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

H. Nii, T. Sanuki, Y. Okayama et al. · 2006 · 22 citations

Engineering, Computer Engineering, Electrical Engineering +14

A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIs

Kazuo Miyashita, Takashi Nakayama, A. Oishi et al. · 2002 · 17 citations

Engineering, Computer Engineering, Electrical Engineering +17