Mobility improvement for 45nm node by combination of optimized stress control and channel orientation design

Abstract

Performance improvement of CMOSFET by adopting <100>-channel direction with high tensile stress gate capping layer (GC liner-SiN) was demonstrated. For pMOSFET, higher hole mobility of <100>-channel and lesser short channel effect (SCE) results in 20% improvement of I/sub on/. In addition, this improvement was not sensitive to local uniaxial strain. For nMOSFET, similar to <110>-channel, 10% improvement of I/sub on/ is realized in <100>-channel with high tensile stress gate capping layer. Thus, this technology can improve the performance of nMOSFET and pMOSFET without introducing specific additional processes for nMOSFET and pMOSFET.