T. Sanuki

High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique

A. Oishi, Osamu Fujii, T. Yokoyama et al. · 2005 · 42 citations

Engineering, Electrical Engineering, Circuit Theory +16

Mobility improvement for 45nm node by combination of optimized stress control and channel orientation design

T. Komoda, A. Oishi, T. Sanuki et al. · 2005 · 42 citations

Engineering, Electrical Engineering, Microelectronics +12

Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique

H. Aikawa, E. Morifuji, T. Sanuki et al. · 2008 · 37 citations

Engineering, Electrical Engineering, Microelectronics +16

Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology

T. Sanuki, A. Oishi, Y. Morimasa et al. · 2004 · 35 citations

Engineering, Electrical Engineering, Microelectronics +16

Cryogenic Operation of 3D Flash Memory for New Applications and Bit Cost Scaling with 6-Bit per Cell (HLC) and Beyond

Yuta Aiba, Hitomi Tanaka, Takashi Maeda et al. · 2021 · 30 citations

Engineering, Computer Engineering, Materials Science +14