Y. Takai

A 1-gb/s/pin 512-mb ddrii sdram using a digital dll and a slew-rate-controlled output buffer

T. Matano, Y. Takai, T. Takahashi et al. · IEEE Journal of Solid-State Circuits · 2003 · 65 citations

Engineering, Computer Engineering, Electrical Engineering +14

250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture

Y. Takai, Masaaki Nagase, M. Kitamura et al. · IEEE Journal of Solid-State Circuits · 1994 · 25 citations

Engineering, Computer Engineering, Electrical Engineering +9

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

T. Matano, Mario Morino, M. Nakamura et al. · 2002 · 14 citations

Engineering, Computer Engineering, Electrical Engineering +14

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

Hironori Fujisawa, M. Nakamura, Y. Takai et al. · IEEE Journal of Solid-State Circuits · 2005 · 12 citations

Engineering, Computer Engineering, Electrical Engineering +15

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

Y. Takai, Masafumi Fujita, K. Nagata et al. · IEEE Journal of Solid-State Circuits · 2000 · 12 citations

Engineering, Computer Engineering, Electrical Engineering +16