250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture

Abstract

A 3.3-V 512-k/spl times/18-b/spl times/2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm/sup 2/, which is the same die size as the conventional DRAM, has been achieved with 0.50-/spl mu/m CMOS process technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>