Proceedings Design, Automation and Test in Europe Conference and Exhibition

Bandwidth-constrained mapping of cores onto NoC architectures

Srinivasan Murali, Giovanni De Micheli · 2004 · 481 citations · Full text

Engineering, Computer Engineering, Computer Science +17

A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation

Kris Tiri, Ingrid Verbauwhede · 2004 · 468 citations

Engineering, Computer Engineering, Electrical Engineering +17

Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip

Mikael Millberg, Erland Nilsson, Rikard Thid et al. · 2004 · 221 citations

Computing, Computer Science, Computer Systems +10

×pipesCompiler: a tool for instantiating application specific networks on chip

Antoine Jalabert, Srinivasan Murali, Luca Benini et al. · 2004 · 161 citations · Full text

Engineering, Computer Engineering, Computer Science +17

A power and performance model for network-on-chip architectures

Nilanjan Banerjee, Pradyumna Vellanki, Karam S. Chatha · 2004 · 115 citations

Engineering, Computer Engineering, Electrical Engineering +17