Combinational Logic Synthesis

Combinational Logic Synthesis is a method in the field of digital circuit design that transforms a high-level logical specification into an optimized network of logic gates or lookup tables implementing the same combinational functionality without memory or feedback.

972

Publications

51.8K

Citations

1.7K

Authors

452

Institutions

Publications per year

2017–2026

89

Authors

1.7K

  1. RK
    Robert K. Brayton

    University of California, Berkeley, United States

    54 publications · 6.5K citations

    35

    h-index

  2. AS
    Alberto Sangiovanni‐Vincentelli

    University of California, Berkeley, United States

    39 publications · 5.1K citations

    28

    h-index

  3. GD
    Giovanni De Micheli

    École Polytechnique Fédérale de Lausanne, Switzerland

    31 publications · 1.3K citations

    21

    h-index

  4. AM
    Alan Mishchenko

    University of California, Berkeley, United States

    29 publications · 1.9K citations

    20

    h-index

  5. MP
    Marek Perkowski

    Portland State University, United States

    24 publications · 789 citations

    17

    h-index

1–5 of 1.7K

Venues

  1. 42

    h-index

  2. IEEE Transactions on Computers

    62 publications · 5.8K citations

    33

    h-index

  3. International Conference on Computer Aided Design

    Conference · 18 publications · 1.6K citations

    15

    h-index

  4. Design Automation Conference

    Conference · 12 publications · 277 citations

    11

    h-index

  5. IEEE Transactions on Electronic Computers

    9 publications · 477 citations

    9

    h-index

1–5