Combinational Logic Synthesis
Combinational Logic Synthesis is a method in the field of digital circuit design that transforms a high-level logical specification into an optimized network of logic gates or lookup tables implementing the same combinational functionality without memory or feedback.
972
Publications
51.8K
Citations
1.7K
Authors
452
Institutions
Publications per year
2017–2026
89
Parents
972
Synthesis and optimization of digital circuits
Choice Reviews Online · 1994 · 2.4K citations
Engineering, Computer Engineering, Electrical Engineering +17
SIS : A System for Sequential Circuit Synthesis
Ellen Sentovich · 1992 · 1.9K citations
Akers · IEEE Transactions on Computers · 1978 · 1.8K citations
1–5 of 972
1.7K
35
h-index
University of California, Berkeley, United States
39 publications · 5.1K citations
28
h-index
École Polytechnique Fédérale de Lausanne, Switzerland
31 publications · 1.3K citations
21
h-index
20
h-index
17
h-index
1–5 of 1.7K
452
University of California, Berkeley
Berkeley, United States
42 h-index
238 publications
26.8K citations
IBM (United States)
Armonk, United States
24 h-index
57 publications
5.3K citations
École Polytechnique Fédérale de Lausanne
Lausanne, Switzerland
20 h-index
74 publications
2.4K citations
Synopsys (United States)
Mountain View, United States
20 h-index
40 publications
2.8K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
20 h-index
59 publications
2.6K citations
University of Illinois Urbana-Champaign
Urbana, United States
18 h-index
52 publications
2.8K citations
Stanford University
Stanford, United States
18 h-index
50 publications
2.9K citations
Princeton University
Princeton, United States
18 h-index
36 publications
1.3K citations
1–8 of 452
95 publications · 7K citations
42
h-index
62 publications · 5.8K citations
33
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Conference · 18 publications · 1.6K citations
15
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Conference · 12 publications · 277 citations
11
h-index
9 publications · 477 citations
9
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1–5