MIS: A Multiple-Level Logic Optimization System

TLDR

MIS is a multilevel logic synthesis and minimization system that supports both interactive and batch-oriented workflows. The paper outlines MIS and details its underlying algorithms. MIS begins with combinational logic extracted from a macrocell description, generates multilevel optimized equations that preserve input‑output behavior, and offers both fast and more optimal area‑minimizing algorithms along with global timing optimization to satisfy system‑level constraints. Examples show the input language for logic and don't‑cares, and industrial chip parts re‑synthesized with MIS achieved better results than equivalent manual designs.

Abstract

MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. MIS starts from the combinational logic extracted, typically, from a high-level description of a macrocell. It produces a multilevel set of optimized logic equations preserving the input-output behavior. The system includes both fast and slower (but more optimal) versions of algorithms for minimizing the area, and global timing optimization algorithms to meet system-level timing constraints. This paper provides an overview of the system and a description of the algorithms used. Included are some examples illustrating an input language used for specifying logic and don't-cares. Parts on an industrial chip have been re-synthesized using MIS with favorable results as compared to equivalent manual designs.